Field
The present disclosure generally relates to the design of photonic integrated circuits (PICs). More specifically, the present disclosure relates to a PIC that includes a surface-normal coupler that couples an optical signal from another PIC.
Related Art
Optical interconnects or links based on silicon photonics have the potential to alleviate inter-chip communication bottlenecks in high-performance computing systems that include a large number of processor chips and memory chips. This is because, relative to electrical interconnects, optical interconnects offer significantly improved: bandwidth, density, power consumption, latency, and range.
Much of the research on silicon photonics has focused on sub-micron silicon-on-insulator (SOI) technologies because they allow both active and passive optical devices to be implemented. Moreover, the use of grating couplers further enables sub-micron silicon-photonic optical links through optical fibers or chip-to-chip direct optical proximity coupling. Using such optical devices, even a multi-chip optical interconnect network with all-to-all full connectivity can be implemented using grating-based surface-normal couplers without any optical waveguide crossing. However, silicon optical waveguides on an SOI platform with a silicon thickness less than 1.5 μm have a different effective index of refraction and group index of refraction for transverse electric (TE) and transverse magnetic (TM) polarization, respectively. Therefore, one of the weaknesses of sub-micron SOI platforms is that most of the optical devices are very polarization-sensitive, which makes it difficult to implement a wavelength-division-multiplexing (WDM) silicon-photonic optical link over fiber.
Alternatively, silicon optical waveguides on a thicker SOI platform (e.g., a silicon layer having a thickness greater than 1.5 μm) can be made with an identical effective index of refraction and group index of refraction for both TE and TM polarizations. Consequently, silicon-photonic optical devices on a thicker SOI platform, e.g., a silicon layer having a thickness of 3 μm, can be polarization-insensitive. Low-loss optical waveguides and other polarization-insensitive WDM optical components for such an SOI platform are available. The recent successful demonstrations of germanium-based high-speed active optical devices on a 3 μm SOI platform, as well as a Franz-Keldysh modulator and a photo-detector, make a thicker SOI platform promising for intra/inter-chip WDM silicon-photonic optical links. However, for a multi-chip application with chip-to-chip interconnects (such as a so-called ‘macrochip’), a compact surface-normal coupler with low loss and broad optical bandwidth is not available for a thicker SOI platform.
In particular, while specially designed grating couplers have been reported for surface-normal coupling for thick SOI platforms with silicon layers having thicknesses of up to 2 μm. However, it is not clear that these grating couplers will be as effective for thicker SOI platforms, such as those with silicon layers having a thickness of 3 μm. Even if the grating couplers work in this regime, the polarization sensitivity of grating couplers may restrict the use of thicker SOI platforms.
For the thicker SOI platforms, it may be possible to utilize a reflecting facet on the optical waveguide for surface-normal coupling. Silicon micro-machining using dry etching of a silicon wafer at an angle can create a reflecting facet at the end of the silicon optical waveguide. When the optical signal in these optical waveguide reaches the reflecting facet etched with a right angle, it may be reflected normal to the surface because of total internal reflection (TIR). While this approach can be implemented as a wafer-scale process, it can be very challenging to create the reflecting facet with good uniformity and repeatability. In principle, laser milling or focused ion beam (FIB) can also be used to create such a reflecting facet on silicon optical waveguides. However, these fabrication techniques are not wafer-scale processes and, thus, are not suitable for low-cost, high-yield volume production.
Hence, what is needed is a surface-normal coupler for use with thicker SOI platforms without the problems described above.